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intrduction to STD80/stdm80 1
table of contents library description....................................................................................................... 1-1 features....................................................................................................................... 1-1 cae support................................................................................................................ 1-2 product family ............................................................................................................. 1-2 internal macrocells.............................................................................................. 1-2 macrofunctions.................................................................................................... 1-2 megafunctions..................................................................................................... 1-2 memory compilers.............................................................................................. 1-2 datapath compilers ............................................................................................ 1-2 input/output cells ............................................................................................... 1-3 v dd /v ss rules and guidelines .................................................................................... 1-6 power dissipation ........................................................................................................ 1-7 propagation delays ..................................................................................................... 1-9 delay model ................................................................................................................. 1-13 testability design methodology ................................................................................... 1-14 maximum fanouts ....................................................................................................... 1-15 product line-up........................................................................................................... 1-22 packages ..................................................................................................................... 1-22 dedicated corner v dd /v ss pads................................................................................. 1-23 external design interface considerations ................................................................... 1-23 crystal oscillator considerations................................................................................. 1-29
introduction to STD80/stdm80 library description sec asic 1-1 STD80/stdm80 library description STD80 and stdm80 are 5v and 3.3v 0.5 m m cmos standard cell libraries supporting triple- and double-layer metal interconnections provided by samsung electronics. every types of internal macrocells and input/output buffers are contained in these cell libraries. with the regard to the current increase of power mixture, 5v-to-3.3v and 3.3v-to-5v convertible cells having a level shifter inside are included in these libraries. in addition, the other interface (cmos, ttl and schmitt trigger) cells are fully equipped for your wide selection. various kinds of macrofunctions, megafunctions, memory and datapath compilers may satisfy the complicated design requirements. moreover, core & megafunction cells such as mpu and dsp, and analog cells are under development. we ensure the product reliability by preventing any possible noise, esd and latch-up ef?ciently. every work operation in a design ?ow has been systematized and automated, and each stage is designed to go through enough reviews and veri?cations. it makes the design work easier and faster, and also prevents any errors or mistakes possible through a design ?ow. features q STD80: 5volt standard cell library stdm80: 3.3volt standard cell library q mixed 5v/3.3v i/o interface q 0.5 m m 5v hcmos technology C double and triple layer metal options q high basic cell usages C up to 700,000 total number of gates C maximum usage: 70% for triple layer metal C maximum usage: 40% for double layer metal q high speed C 0.2 ns (for STD80) and 0.3ns (for stdm80) delay of 2-input nand with fanout = 2 q fully con?gurable ram, rom and dpram C up to 512k-bit rom available C up to 128k-bit ram available C up to 64k-bit dpram available q con?gurable datapath elements available C 4 ~ 128-bit bus width q operating temperature (t a ) C commercial range: 0?c to +70?c C industrial range: C40?c to +85?c q esd and latch-up protection C esd: 2000v (min.) C latch-up: 300ma (min.) q selectable output current drive capability C 1/2/4/8/12/16/20/24ma available for 5v C 1/2/4/6/8/10/12/16ma available for 3.3v q ttl, cmos, lvttl, lvcmos and schmitt trigger i/os q x-tal oscillators q pci, pcmcia buffers q gtl, ntl, cardbus, scsi, pecl, usb under-developed q various package options q fully integrated cad software support C verilog, viewlogic, mentor and synopsys
cae support introduction to STD80/stdm80 STD80/stdm80 1-2 sec asic cae support STD80/stdm80 supports popular design platforms and environments such as verilog, viewlogic, mentor and synopsys for front-end logic design capture and simulation, and arccell for back-end placement and routing. for a high simulation accuracy, STD80/stdm80 uses a proprietary delay calculator. cell delay calculations are based on a matrix of delay parameters for each macrocell, and signal interconnection delay is based on the rc tree analysis. product family STD80/stdm80 library include the following design elements: (a) internal macrocells (b) input/output cells (c) macrofunctions (d) megafunctions (e) memory compilers (f) datapath compilers (g) jtag boundary scans. < internal macrocells > macrocells are the lowest level of logic functions such as nand, nor and ?ip-?op used for logic designs. there are about 300 different types of internal macrocells. they usually come in two levels of drive strength (1x and 2x). these macrocells have many levels of representationslogic symbol, logic model, timing model, transistor schematic, hspice netlist, physical layout, and placement and routing model. < macrofunctions > macrofunctions are netlists of logic function which have the complexity of a standard msi circuit. macrofunctions are logic building blocks. there are 44 kinds of 74xx (ttl) compatible functions in this library. < megafunctions > megafunctions are also netlists of logic function, but with a high logic complexity of a standard lsi circuit. multipliers, barrel shifters, 82xx intel functions, etc. are supported in this library. < memory compilers> memory compilers of stdl80 consist of two roms (synchronous contact programmable and synchronous diffusion programmable), three single-port rams (synchronous and asynchronous) and three dual-port rams (synchronous and asynchronous). in addition, a register file and a fifo are under-developed. < datapath compilers > datapath compilers of STD80/stdm80 consist of 16 macro cells (adder, alu, multiplier, etc.) and 14 primitive cells (nand, nor, dff, latch, mux, etc.)
introduction to STD80/stdm80 < input/output cells > sec asic 1-3 STD80/stdm80 < input/output cells > there are about one thousand different i/o buffers. each i/o cell is implemented solely on the basic i/o cell architecture which forms the periphery of the masterslice. a test logic is provided to enable the ef?cient parametric (threshold voltage) testing on input buffers including cmos and ttl level converters, schmitt trigger input buffers, clock drivers and oscillator buffers. pull-up and pull-down resistors are optional features. three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1ma to 24ma for 5v drive and 1ma to 16ma for 3.3v drive.two levels of slew rate controls are provided for each buffer type (except 1ma and 2ma buffers) to reduce output power/ground bus noise and signal ringing, especially in simultaneous switching outputs. bi-directional buffers are combinations of input buffers and output buffers (tri-state or open drain) in a single unit. the i/o structure has been fully characterized for esd protection and latch-up resistance. for users convenience, STD80/stdm80 library provides with three options of pull-down and pull-up resistances respectively. they are 50k w , 100k w , and 200k w (the default value is 100k w ). i/o cell drive options to provide designers with the greater ?exibility, each i/o buffer can be selected among various current levels (e.g., 1ma, 2ma, ..., 24ma). the choice of current-level for i/o buffers affects their propagation delay and current noise. the slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. the output edge rate can be slowed down by selecting the high slew rate control cells. STD80/stdm80 provides three different sets of output slew rate controls. only one i/o slot is required for any slew rate control options. 5v/3.3v mixed i/o cells when designers intend to make transitions from 5v supplies to low voltage system, STD80 offers a solution of interfacing problems encountered in mixed 5v/3v environment. this solution provides great ?exibility to different devices communicating each other. pci and pcmcia buffers are also available in this solution. you can see this in the following ?gure. figure 1-1. 5v/3.3v mixed i/o cells in STD80 in stdm80, level shifters are available to provide internal 3v core with great ?exibility when it interfaces with a 5v device. refer to the ?gure below. figure 1-2. 5v/3.3v mixed i/o cells in stdm80 pci buffers in addition to input, output, bi-directional, slew rate controlled and schmitt trigger i/o buffers, sec asic now offers pci (peripheral component interconnect) i/o buffers. pci is expected to be better suited to the more complex and feature-rich design than the existing local bus standards. 5v, 3.3v and universal pci buffers are included in the library. 3.3v level shifter 5v internal 5v STD80 i/o cells 3.3v level shifter 5v STD80 i/o cells operation 3.3v 5v internal 3.3v stdm80 i/o cells 3.3v 5v stdm80 i/o cells level shifter level shifter operation
< input/output cells > introduction to STD80/stdm80 STD80/stdm80 1-4 sec asic pecl sec asics pecl (positive emitter coupled logic) buffer having 155mhz operating frequency is suited to atm interface. it supports two voltage source modes; 5v and 3.3v. the voltage swing level is about 0.8v, being similar to that of ecl, and the external terminator is needed. its main features are the same as ecl; low noise, high speed and single ended/differential function. in case of differential transmission, the external terminator is shown in the following ?gure. figure 1-3. twisted pair termination techniques gtl (gunning transceiver logic) gtl and gtl+ interface i/os are useful for implementing highly reliable system, satisfying fast and low-powered signal transfers and reducing noise in a switching circuitry. in all 0.5 m m cell libraries in sec asic, gtl interface is fully supported. figure 1-4. gtl interface lvds lvds (low voltage differential signals) buffer for sci (scalable coherent interface) system, shown in the following ?gure, enables high speed i/o interface with sec asics high frequency pll. this structure is designed for high speed point-to-point unidirectional interface. its main characteristics are much the same as ecls differential mode; low noise generation, high noise immunity and low level signalling. figure 1-5. lvds interface r pd r pd r 1 v ee v ee z o r 1 = z o standard twisted pair termination r 1 r 1 v tt v tt z o r 1 = z o /2 parallel twisted pair termination r 1 r 2 v ee z o r 1 = z o /2 thevenin twisted pair termination r 3 v t v t logic rcvr vref logic rcvr vref logic rcvr vref r t r t 100 w a v oa v ob b a b v ia v ib v gpd receiver interconnect driver
introduction to STD80/stdm80 < input/output cells > sec asic 1-5 STD80/stdm80 lvttl/lvcmos low voltage ttl and low voltage cmos i/o buffers have various kinds of applications as normal ttl and cmos i/o sets. their key features are low voltage swing and low noise. input voltage level is 5v compatible. output high voltage is 2.4v ~ 3.5v in lvttl and vddC0.2v in lvcmos. scsi scsi is widely used to extend peripherals, requires external terminator. sec asic supports scsi-3 fast-20 parallel interface and scsi-3 parallel interface only in STD80. both of them have fail-safe function. scsi buffer is two times as big as normal buffers. pcmcia pcmcia (personnel computer memory card industry association) buffers guarantees an accurate logic level even when the internal or external voltage source level of a chip changes between 5v and 3.3v. this buffers are designed for 16-bit external extension card of notebook pc. cardbus buffers cardbus i/o buffers have 3.3v 32-bit bus width and 33mhz of transmission speed. they are for external cardbus type of extension card of notebook pc. usb speci?cation established late in 1995 is a good solution for this problem, providing facile method of an expansion. sec asic offers usb interfaced buffers in the 0.5 m m technology. usb is applicable only in std cells. usb (universal serial bus) various kinds of peripheral equipments such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. however, it is not easy to connect and use them properly in the computer. figure 1-6. full speed device cable and resistor connections figure 1-7. low speed device cable and resistor connections r1 r1 d+ dC f.s./l.s. usb transceiver twisted pair shielded host or hub port r2 d+ dC f.s. usb transceiver hub port or full speed function 5 meters max. z0 = 90 w 15% r1 = 15k w r2 = 1.5k w r1 r1 d+ dC f.s./l.s. usb transceiver untwisted, unshielded host or hub port r2 d+ dC l.s. usb transceiver low speed function 3 meters max. r1 = 15k w r2 = 1.5k w slow slew rate buffer
vdd/vss rules and guidelines introduction to STD80/stdm80 STD80/stdm80 1-6 sec asic v dd /v ss rules and guidelines there are three types of v dd and v ss in STD80/stdm80, each with its related bus and pad cells. to support the use of mixed voltage, two different v dd types are needed for 5v and 3.3v respectively. (1) core logic C vssi, vdd5i (for 5v) (2) input buffers (usable when requested) C vssp, vdd5p (for 5v), vdd3p (for 3.3v) (3) output buffers C vsso, vdd5o (for 5v), vdd3o (for 3.3v) the number of v dd and v ss pads required for a speci?c design depends on the following factors: ? number of input and output buffers ? number of simultaneous switching inputs ? number of simultaneous switching outputs ? number of used gates and simultaneous switching gates ? operating frequency of the design. core logic v ss bus and vssi pad allocation guidelines the purpose of these guidelines is to ensure that v dd /v ss bounce caused by a simultaneous gate switching is kept to minimum. the voltage bounce on the power bus can have a negative impact on a gate-switching speed and even on the functionality of macrocells like ?ip-?ops and latches in an extreme case. because of variations in package inductance, the number of v dd /v ss pads required for a speci?c design is the function of the operating frequency of a chip, i.e., designs operating at high frequency should use more v dd /v ss pads. ?v dd bus width and pad requirements are half of v ss . ?v dd /v ss buses and pads should be distributed evenly in the core and on all sides of the chip. ? whenever possible, at least one vssi pad should be used on each side of the chip. ? the total number of core logic v dd pads required is half of vssi. the number of vssi pads required for a design can be calculated from the following expression: g x s x f x 2.00eC5 ,where g = total number of used gates, s = % of simultaneous switching gates, f = switching frequency in mhz. input buffer v dd /v ss pad allocation guidelines these guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. ? one vssp is required to support 32 input buffers, and one input buffer v dd can support up to 64 inputs. ? for simultaneous switching inputs, one vssp pad is required for every 20 inputs, and one input buffer v dd pad for every 40 inputs. ? input buffer v ss /v dd pads should be placed in such a way that they equally divide the input buffers on either side. output buffer v dd /v ss pad allocation guidelines the number of vsso pads required for a device can be calculated from the following expressions. in 5v ? (i ol simultaneous switching outputs ) / 40 + ? (i ol normal outputs ) / 64 in 3.3v ? (i ol simultaneous switching outputs ) / 50 + ? (i ol normal outputs ) / 80 ? the total number of output buffer v dd pads required is half of vsso. ? output buffer v ss /v dd pads should be placed in such a way that output buffers are equally divided on either side.
introduction to STD80/stdm80 power dissipation sec asic 1-7 STD80/stdm80 power dissipation estimation of power dissipation in cmos circuit cmos circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. however, the recent revolution in a cmos technology that allows very high gate density has changed the way the power dissipation should be understood. the power dissipation in a cmos circuit is affected by various factors such as the number of gates, a switching frequency, the loading on the output of a gate, and so on. power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. propagation delays and a reliability of the device also depend on the power dissipation which determines the temperature at which the die operates. to obtain a high speed and a reliability, designers must estimate the power dissipation of the device accurately and determine the appropriate environments including packages and system cooling methods. this section describes the concept of two types of power dissipation (static and dynamic) in a cmos circuit, the method of calculating them in the sec STD80/stdm80 library, and ?nally their relationship with a temperature. static (dc) power dissipation there are two types of static or dc current contributing to the total static power dissipation in cmos circuits. one is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. there is no dc current path from power to ground in a cmos because one of the transistor pair is always off, therefore, no static current except the leakage current ?ows through the internal gates of the device. the amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. the other is dc current that ?ows through the input and output buffers when the circuit is interfaced with other devices, especially ttl. the current of pull-up/pull-down transistor included in the input buffers is about 50 m a typically, which is also negligible. therefore, only dc current that the output buffers source or sink has to be counted to estimate the total static power dissipation. dc power dissipation of ttl output and bi-directional buffers is determined by the following formula: p dc_ttl_ output = ? (v ol x i ol x t l ) + ? ((v dd C v oh ) x i oh x t h ) ,where t h = t high / t, t l + t h = 1. dynamic (ac) power dissipation when a cmos gate changes its state, it draws switching current as a result of charging or discharging of a node capacitance, c l . the energy associated with the switching current for a node capacitance, c l , is 1 / 2 x (c l x v dd 2 ) ,where v dd is a power supply voltage. the switching occurs twice per cycle for periodic signals: once for charging a capacitance and once for discharging it. hence, the dynamic power dissipation due to the switching current is the energy divided by the clock period and multiplied by the factor of two, or c l x v dd x v dd / t ,where t is a clock period. as shown above, it is quite straight forward to calculate the dynamic power dissipation for a single gate. the dynamic power dissipation for an entire chip is, however, much more complicated to estimate since it depends on the degree of switching activity of the circuit. sec has found that the degree of switching activity is 20% on the average and recommends to use this number to estimate the total dynamic power dissipation.
power dissipation introduction to STD80/stdm80 STD80/stdm80 1-8 sec asic power dissipation in STD80/stdm80 this section describes the equations on how to estimate the power dissipation in STD80/stdm80. as explained in the previous section, the total power dissipation (p total ) consists of static power dissipation (p dc ) and dynamic power dissipation (p ac ). p total = p dc + p ac since only output buffers contribute to the static power dissipation, p dc = p dc_output ,where p dc output is the static power dissipated when output buffers source or sink. the dynamic power dissipation is caused by three components: input buffers (p ac_input ), output buffers (p ac_output ), and internal cells (p ac_internal ). p ac = p ac_ input + p ac_output + p ac_internal each term mentioned above is characterized by the following equations: in STD80, p dc_output = 150 x i ol x n_output [ m w] p ac_input = 23 x n_input x f x s [ m w] p ac_output = 25 x n_output x f x s x c [ m w] p ac_internal = 2.3 x n_internal x f x s [ m w] in stdm80, p dc_output = 150 x i ol x n_output [ m w] p ac_input = 9.8 x n_input x f x s [ m w] p ac_output = 25 x n_output x f x s x c [ m w] p ac_internal = 1.2 x n_internal x f x s [ m w] ,where i ol is source and sink current of output buffers in ma, n_output is the number of output buffers used, n_input is the number of input buffers used, n_internal is the number of internal cells used, f is the maximum operation frequency in mhz, s is the estimated degree of a switching activity (typically 0.2), c is the output load capacitance in pf. temperature and power dissipation the total power dissipation, p total can be used to ?nd out the device temperature by the following equation: q ja = (t j C t a ) / p total ,where q ja is the thermal impedance, t j is the junction temperature of the device, t a is the ambient temperature. thermal impedances of the sec packages are given in the following table. the junction temperature, obtained by multiplying p total by the appropriate q ja and adding t a , determines the derating factor for the propagation delays and also indicates the reliability measures. hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. table 1-1. thermal impedances of sec packages maximum junction temperature (t j ) the allowable maximum junction temperatures for plastic and ceramic packages are as follows: junction temperature for plastic package 125 c junction temperature for ceramic package 150 c. qfp pin number 64 80 100 120 160 208 240 q ja [ c/w] 60 60 60 50 50 40 40
introduction to STD80/stdm80 propagation delays sec asic 1-9 STD80/stdm80 propagation delays interconnection wire length, temperature and supply voltage are the chief factors affecting propagation delays. wire length load the loading due to interconnection wire length can be estimated with the following expression. the result is given in terms of number of equivalent standard loads. c wl = c fo ,where c fo = number of fanouts in a standard load, a = area of block size in mm 2 , c wl = number of equivalent standard loads due to an interconnection, e.g., c fo = 7 (standard load), a = 25mm 2 , c wl = 5.8 (standard load). temperature and supply voltage the next ?gure describes propagation delay correction factors (k t , k v ) as a function of on-chip junction temperature (t j ) as well as supply voltage (v dd ). as a result of increasing cmos power dissipation, ambient and junction temperature are generally not the same. the temperature of the die inside the package (junction temperature, t j ), is calculated using chip power dissipation and the thermal resistance to ambient temperature ( q ja ) of the package. information on package thermal performance can be obtained from sec application engineers. figure 1-8. effect of temperature and supply voltage on propagation delay 0.049 a 0.48 + () 0.079 a 0.33 + + temperature (t j ) k t 1.10 1.08 1.00 0.96 0.90 C40 0 70 25 85 1.18 125 ( c) supply voltage (v dd ) 1.07 1.00 0.94 4.5 5.0 5.5 (volt) k v 1.04 0.97 4.75 5.25 1.19 1.00 3.0 3.6 (volt) k v 1.08 0.94 2.7 3.3 1.12 1.09 1.00 0.95 0.87 1.21 STD80 stdm80 STD80 stdm80
propagation delays introduction to STD80/stdm80 STD80/stdm80 1-10 sec asic best and worst case conditions a circuit should be designed to operate properly within a given speci?cation level, either commercial or industrial. it is recommended that circuits be simulated for best case, normal case, and worst case conditions at each speci?cation level. the following expressions also allow for the effect of process variation on circuit performance. best case: t bc = k pbc x k t x k v x t nom = k bc x t nom worst case: t wc = k pwc x k t x k v x t nom = k wc x t nom ,where t bc = best case propagation delay t wc = worst case propagation delay t nom = normal propagation delay (t j = 25 o c, v dd = 5v and typical process) k pwc = worst case process correction factor k pbc = best case process correction factor with above equations, we can calculate the multipliers of k wc and k bc as follows. table 1-2. STD80 best case delay table 1-3. STD80 worst case delay table 1-4. stdm80 best case delay table 1-5. stdm80 worst case delay derating factors of STD80/stdm80 the multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. nominal data are provided for conditions of v dd = 5v, t a = 25 c and typical process. the derating factors of STD80/stdm80 are as follows. table 1-6. STD80/stdm80 process derating factor table 1-7. STD80 temperature derating factor table 1-8. stdm80 temperature derating factor table 1-9. STD80 voltage derating factor (k v ) table 1-10. stdm80 voltage derating factor (k v ) application best case delay parameter k bc v dd t j proc. industrial 5.5v C40 o c min. 0.51 commercial 5.25v 0 o c min. 0.56 application worst case delay parameter k wc v dd t j proc. industrial 4.5v 125 o c max. 1.77 commercial 4.75v 115 o c max. 1.69 application best case delay parameter k bc v dd t j proc. industrial 3.6v C40 o c min. 0.49 commercial 3.6v 0 o c max. 0.52 application worst case delay parameter k wc v dd t j proc. industrial 2.7v 125 o c max. 1.97 commercial 3.0v 115 o c max. 1.77 process factor (k p ) slow typ. fast 1.40 1.00 0.60 temp. ( o c) 125 85 70 25 0 C40 k t 1.21 1.12 1.09 1.00 0.95 0.87 temp. ( o c) 125 85 70 25 0 C40 k t 1.18 1.10 1.08 1.00 0.96 0.90 voltage (v) 5.5 5.25 5 4.75 4.5 k v 0.94 0.97 1.00 1.04 1.07 voltage (v) 3.6 3.3 3.0 2.7 k v 0.94 1.00 1.08 1.19
introduction to STD80/stdm80 propagation delays sec asic 1-11 STD80/stdm80 timing parameters this section discusses issues involving timing parameters for primitive cells. rise / fall times the de?nition of rise time (t r ) and fall time (t f ) is shown in the following ?gure. figure 1-9. rise and fall times setup / hold times setup time (t su ) is a minimum period in which the input data to a ?ip-?op or a latch must be stable before the active edge of the clock occurs. hold time (t hd ) is a minimum period in which the input data to a ?ip-?op or a latch must remain stable after the active edge of the clock has occurred. the next ?gure shows the relationship between setup and hold times for a standard ?ip-?op triggered on the rising edge of the clock. figure 1-10. setup and hold times minimum pulse widths minimum clock pulse widths (t pwh , t pwl ) are the time intervals during a clock signal is high or low, so that it ensures proper operation of a ?ip-?op or a latch. figure 1-11. minimum pulse width recovery times recovery time (t rc ) is the minimum time after an asynchronous pin is disabled that an active clock edge will propagate data from input to output. if the active edge or clock occurs before the speci?ed recovery time, the input data will not propagate. figure 1-12. recovery time t r t f 10% 90% 90% 10% v dd d ck t su t hd d ck q t pwh d rb ck q t rc
propagation delays introduction to STD80/stdm80 STD80/stdm80 1-12 sec asic propagation delays a delay for a macrocell is considered to be a rising delay (t plh ) if the signal on the output pin is rising. for a rising input and a rising output, the rising delay is the interval between the times the input becomes 50% of supply voltage (v dd ) and the output becomes 50% of v dd . if the input is falling and the output is rising, the rising delay is the interval between the times the input falls to 50% of v dd and the output rises to 50% of v dd . the converse is true for a falling delay (t phl ). figure 1-13. propagation delay proper use of buffers figure 1-14. average gate delay in STD80 shows the average propagation delays of an internal inverter (iv), an 8x inverter (ivd8), a normal clock driver (ck2), and a high clock driver (ck12) in STD80. note that transistors uses in i/o slots are larger and have on channel resistance about one order of magnitude lower than those of the n and p channel transistors in primitive cells. this makes them likely candidates for use as buffers for high fanout signals. for example, ck2 and ck12 buffers require one i/o slot location. both can be used as high fanout internal buffers. figure 1-14. average gate delay in STD80 one caution, emphasized in figure 1-15. use of i/o slot for an internal buffer, shows that if you route to a buffer that uses an i/o slot from an internal element and back into internal logic, the additional wiring needed could increase propagation delays materially. higher drive strength internal cells may be more appropriate than i/o slot buffers. realize also that using i/o slot cells for internal buffering removes those locations for use as external i/os and uses two wiring channels, thereby increasing routability congestion on masterslice products. figure 1-15. use of i/o slot for an internal buffer 50% 50% t plh 50% 50% t plh 50% 50% t phl 50% 50% t phl v dd 1.5 1.0 0.5 0 10 40 80 160 320 fanout [number] iv ivd8 ck2 ck12 average delay [ns] clock driver using i/o slot high fanout long wire
introduction to STD80/stdm80 delay model sec asic 1-13 STD80/stdm80 delay model the asic timing characteristics consist of the following components: ? cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. ? interconnection wire delay across the metal lines. ? timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. ? derating factors for junction temperature, power supply voltage, and process variations. timing model for STD80/stdm80 focuses on how to characterize cell propagation delay time accurately. to accomplish this goal, 2-dimensional table look-up delay model has been adopted. the index variables of this table are input waveform slope and output load capacitance. see the ?gure below. sec asic design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.5 m m cell-based products. figure 1-16. 2-dimensional table delay model the table 1-11. table delay model example shows an example of this model for 2-input nand cell. the data in this table are high-to-low transition delay times from one of the two input pins to output pin. the number of points and values of the index variables can differ for each cell. table 1-11. table delay model example notice that 4-by-4 table is used. delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. this general table delay model provides great ?exibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. the other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. the delay time due to the interconnection wire can be separated into two components. one is the signal propagation delay time across the metal lines. this delay time component is computed through conventional rc analysis based on ? -model. the other is an additional delay on the driving cell due to the wire load. the traditional way to compute this is based on the lumped capacitance model, ignoring wire resistance. for sub-micron technology, this approximation cannot be accepted any more. the wire resistance has a shielding effect on the driving cell from load capacitances. an effective capacitance c eff , a single capacitance approximating distributed interconnection wire resistance and capacitance, is derived, as illustrated in the following ?gure. the compensation factor k, extracted for each cell, is a function of the length of interconnection wires and the layout topology. all these effects are merged to determine the effective capacitance and this value is used as an index of the table delay model. figure 1-17. concept of effect capacitance propagation delay [ns] input waveform slope [ns] load cap [pf] 1.5 1.0 0.5 1.0 2.0 3.0 0.4 0.8 1.2 0.03 0.13 0.53 1.32 0.10 0.07 0.14 0.42 0.97 0.30 0.08 0.17 0.45 1.02 0.80 0.06 0.18 0.51 1.07 1.60 0.01 0.18 0.60 1.18 c eff = f (k, cload) cap. slope
testability design methodology introduction to STD80/stdm80 STD80/stdm80 1-14 sec asic the ?gure below summarizes the features of sec asics delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used. the slopes (t r , t f ) and delay times (t plh , t phl ) of all cell instances are calculated recursively. the input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. a pin to pin delays of cells and interconnection wires are supported. ? the effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. figure 1-18. features of delay model testability design methodology scan design ? multiplexed scan ?ip-?op that minimizes the area or delay overhead needed to implement scan design ? automated design rules checking, scan insertion, and test pattern generation ? high fault coverage on synchronous designs boundary-scan ? ieee std 1149.1 ? 5 types of jtag boundary-scan cells ? boundary-scan description language (bsdl) description for board testing ? combination with internal scan design s1 s3 s2 co1 co2 co3 ck q d a_y b_y ? ? a mux scannable register device identity register bypass register instruction register ta p controller system logic tdi tms tck tdo test access port mux boundary scan path
introduction to STD80/stdm80 maximum fanouts sec asic 1-15 STD80/stdm80 maximum fanouts internal macrocells the maximum fanouts for STD80/stdm80 primitive cells are as follows. note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.44ns (STD80)/0.39ns (stdm80). depending on the rise and fall times, the maximum fanout limitations can be varied case by case. in the following table the maximum fanout values for all pins of STD80/stdm80 internal macrocells are listed. table 1-12. maximum fanouts of internal macrocells (when t r /t f = 0.44ns (STD80)/0.39ns (stdm80)) cell name output pin maximum fanout STD80 stdm80 logic cells ad2 y 49 28 ad2d2 y 106 59 ad3 y 49 28 ad3d3 y 161 84 ad4 y 49 28 ad4d2 y 105 58 ad5 y 38 17 ad5d2 y 78 34 nd2 y 45 23 nd2d2 y 95 48 nd3 y 30 15 nd3d2 y 63 30 nd4 y 23 11 nd4d2 y 47 22 nd5 y 18 7 nd5d2 y 36 16 nd6 y 49 28 nd6d2 y 104 55 nd8 y 49 28 nd8d2 y 105 56 nr2 y 40 17 nr2d2 y 87 37 nr3 y 25 11 nr3d2 y 54 23 nr4 y 18 7 nr4d2 y 38 15 nr5 y 49 28 nr5d2 y 104 59 nr6 y 49 28 nr6d2 y 104 58 nr8 y 49 28 nr8d2 y 104 58 or2 y 49 28 or2d2 y 104 55 or3 y 49 26 or3d3 y 147 71 or4 y 43 22 or4d2 y 89 44 or5 y 40 21 or5d2 y 89 45 xn2 y 49 27 xn2d2 y 103 54 xn3 y 47 25 xn3d3 y 134 65 xo2 y 49 28 xo2d2 y 102 55 xo3 y 47 25 xo3d3 y 134 65 ao21 y 30 15 ao21d2 y 64 31 ao211 y 22 9 ao211d2 y 44 18 ao22 y 28 13 ao22d2 y 57 27 ao22a y 27 13 ao22d2a y 55 27 ao222 y 21 8 ao222d2 y 105 59 ao222a y 26 10 ao222d2a y 52 21 ao33 y 18 7 ao33d2 y 106 58 ao333 y 15 4 ao333d2 y 107 60 oa21 y 29 15 oa21d2 y 61 31 oa211 y 20 9 oa211d2 y 40 19 oa22 y 28 14 oa22d2 y 59 29 cell name output pin maximum fanout STD80 stdm80
maximum fanouts introduction to STD80/stdm80 STD80/stdm80 1-16 sec asic oa22a y 29 15 oa22d2a y 59 31 oa2222 y 49 28 oa2222d2 y 104 55 dl1d2 y 105 60 dl1d4 y 222 113 dl2d2 y 108 60 dl2d4 y 219 114 dl3d2 y 109 61 dl3d4 y 226 111 dl4d2 y 110 61 dl4d4 y 228 110 dl5d2 y 110 60 dl5d4 y 228 109 dl10d2 y 105 53 dl10d4 y 207 97 iv y 53 29 ivd2 y 114 65 ivd3 y 175 101 ivd4 y 231 144 ivd6 y 324 190 ivd8 y 403 234 iva y 53 29 ivd2a y 114 65 ivd3a y 175 101 ivd4a y 231 144 ivcd11 y 51 27 yn 53 29 ivcd13 y 47 24 yn 175 100 ivcd22 y 117 62 yn 114 65 ivcd26 y 101 53 yn 324 190 ivcd44 y 259 162 yn 231 144 ivt y 43 23 ivtd2 y 93 48 ivtd4 y 177 90 ivtd8 y 323 179 ivtn y 43 22 ivtnd2 y 87 46 ivtnd4 y 173 85 cell name output pin maximum fanout STD80 stdm80 ivtnd8 y 336 158 nid y 49 28 nid2 y 106 59 nid3 y 161 90 nid4 y 222 121 nid6 y 331 163 nid8 y 438 209 nit y 43 23 nitd2 y 91 47 nitd4 y 180 96 nitd8 y 323 203 nitn y 43 23 nitnd2 y 88 46 nitnd4 y 176 88 nitnd8 y 324 158 flip-flops fd1 all pins 49 28 fd1d2 q 105 58 qn 107 60 fd1cs q 49 28 qn 49 27 fd1csd2 q 105 58 qn 104 55 fd1s all pins 49 28 fd1sd2 q 105 58 qn 106 60 fd1q q 49 28 fd1qd2 q 107 59 fd1x2 all pins 49 28 fd1x4 all pins 49 28 yfd1 q 49 26 qn 43 24 yfd1d2 q 105 53 qn 90 49 fd2 all pins 49 28 fd2d2 q 106 58 qn 109 60 fd2cs all pins 49 27 fd2csd2 q 105 58 qn 106 55 fd2s all pins 49 28 fd2sd2 q 106 58 qn 108 60 cell name output pin maximum fanout STD80 stdm80
introduction to STD80/stdm80 maximum fanouts sec asic 1-17 STD80/stdm80 fd2q q 49 28 fd2qd2 q 107 58 fd2x2 all pins 49 28 fd2x4 all pins 49 28 yfd2 q 48 26 qn 40 21 yfd2d2 q 103 51 qn 80 42 fd2t q 49 27 z2815 fd2td2 q 106 58 z5226 fd2tcs q 48 27 z2812 fd2tcsd2 q 104 57 z5226 fd2ts q 49 27 z2812 fd2tsd2 q 106 58 z5226 fd3 all pins 49 28 fd3d2 q 107 58 qn 107 59 fd3cs q 49 28 qn 49 27 fd3csd2 q 106 59 qn 105 55 fd3s all pins 49 28 fd3sd2 q 106 59 qn 106 58 fd3q q 49 28 fd3qd2 q 106 59 fd3x2 all pins 49 28 fd3x4 all pins 49 28 yfd3 q 43 22 qn 43 24 yfd3d2 q 89 42 qn 89 49 fd4 q 49 27 qn 49 28 fd4d2 all pins 106 58 fd4cs all pins 49 27 cell name output pin maximum fanout STD80 stdm80 fd4csd2 q 106 58 qn 106 55 fd4s all pins 49 28 fd4sd2 all pins 106 58 fd4q q 49 28 fd4qd2 q 106 59 fd4x2 all pins 49 28 fd4x4 qn 49 27 qnn 49 28 yfd4 q 43 22 qn 39 20 yfd4d2 q 88 41 qn 80 42 fd5 all pins 49 28 fd5d2 q 105 60 qn 106 59 fd5s all pins 49 28 fd5sd2 q 105 58 qn 106 59 fd5x4 all pins 49 28 fd6 all pins 49 28 fd6d2 q 105 58 qn 106 61 fd6s all pins 49 28 fd6sd2 q 106 58 qn 108 60 fd7 all pins 49 28 fd7d2 q 106 59 qn 106 58 fd7s all pins 49 28 fd7sd2 all pins 106 58 fd8 q 49 27 qn 49 28 fd8d2 q 106 58 qn 105 58 fd8s all pins 49 28 fd8sd2 q 106 59 qn 106 58 fds2 all pins 59 28 fds2d2 q 105 58 qn 106 60 fds2cs q 49 28 qn 49 27 cell name output pin maximum fanout STD80 stdm80
maximum fanouts introduction to STD80/stdm80 STD80/stdm80 1-18 sec asic fds2csd2 q 105 58 qn 105 55 fds2s all pins 49 28 fds2sd2 q 106 60 qn 105 59 fds3 all pins 49 28 fds3d2 q 106 60 qn 105 59 fg1 all pins 49 28 fg1x4 all pins 49 28 fg2 all pins 49 28 fg2x4 all pins 49 28 fj1 all pins 49 28 fj1d2 q 105 56 fj1d2 qn 104 58 fj1s q 50 28 qn 49 28 fj1sd2 q 105 56 qn 107 59 fj2 q 50 28 qn 49 28 fj2d2 q 105 57 qn 106 59 fj2s q 50 28 qn 49 28 fj2sd2 q 106 56 qn 109 61 fj4 q 50 28 qn 49 27 fj4d2 q 105 56 qn 106 58 fj4s q 50 28 qn 49 28 fj4sd2 q 106 56 qn 106 58 ft2 all pins 49 28 ft2d2 q 106 57 qn 108 60 ft3 all pins 49 28 ft3d2 q 107 59 qn 106 58 latches ld1 all pins 49 28 cell name output pin maximum fanout STD80 stdm80 ld1d2 q 106 60 qn 105 58 ld1s all pins 49 28 ld1sd2 q 106 60 qn 106 58 ld1q q 49 28 ld1qd2 q 104 59 ld1x4 all pins 49 28 ld1x4d2 qn 106 59 qnn 106 58 yld1 q 43 24 qn 51 28 yld1d2 q 89 50 qn 114 61 ld1a q 43 23 ld1b qn 15 5 zn 43 23 ld2 all pins 49 28 ld2d2 q 105 58 qn 108 60 ld2q q 49 28 ld2qd2 q 107 59 yld2 q 42 22 qn 44 22 yld2d2 q 44 23 qn 96 47 ld3 all pins 49 28 ld3d2 q 108 60 qn 106 58 ld4 q 49 28 qn 49 27 ld4d2 q 107 58 qn 105 58 ld5 all pins 49 28 ld5d2 q 106 59 qn 105 58 ld5s all pins 49 28 ld5sd2 q 106 59 qn 105 58 ld5x4 all pins 49 28 ld5x4d2 qn 106 59 qnn 106 58 ld6 all pins 49 28 cell name output pin maximum fanout STD80 stdm80
introduction to STD80/stdm80 maximum fanouts sec asic 1-19 STD80/stdm80 ld6d2 q 106 58 qn 108 60 ld7 all pins 49 28 ld7d2 q 108 60 qn 106 58 ld8 q 49 28 qn 49 27 ld8d2 q 107 58 qn 105 58 lds2 all pins 49 28 lds6 all pins 49 28 ls0 all pins 39 20 ls0d2 all pins 78 40 ls1 all pins 18 8 ls2 all pins 39 20 bus holder busholder y 10,000 10,000 internal clock drivers ck2 y fig 1-19 (a) fig 1-20 (a) ck4 y fig 1-19 (b) fig 1-20 (b) ck6 y C fig 1-20 (c) ck8 y fig 1-19 (c) fig 1-20 (d) ck12 y fig 1-19 (d) C decoders dc4 all pins 49 28 dc4i yn(0/2) 43 23 yn(1/3) 45 23 dc8i all pins 30 15 adders fa s 49 28 co 49 27 fad2 s 103 55 co 103 54 ha s 49 27 co 49 28 had2 s 103 54 co 106 59 multiplexers mx2 y 49 28 mx2d3 y 152 76 mx2x4 all pins 49 28 ymx2 y 49 28 ymx2d2 y 102 59 cell name output pin maximum fanout STD80 stdm80 mx2i yn 28 13 mx2id2 yn 104 59 mx2ia yn 28 13 mx2id2a yn 104 59 mx2ix4 all pins 28 13 mx3i yn 49 28 mx3id2 yn 104 59 mx4 y 48 26 mx4d2 y 96 48 ymx4 y 49 27 ymx4d2 y 102 33 mx5 y 49 27 mx5d2 y 102 55 mx8 y 45 22 mx8d2 y 86 41 ymx8 y 49 27 ymx8d2 y 102 53 cell name output pin maximum fanout STD80 stdm80
maximum fanouts introduction to STD80/stdm80 STD80/stdm80 1-20 sec asic i/o cells the maximum fanouts for 5v and 3.3v i/o cells are as follows when the rise and fall times of the input signal is 0.40ns. the graphs for fanout vs. frequency curve of STD80/stdm80 internal/input clock drivers are shown in the next page. table 1-13. maximum fanouts of i/o cells (when t r /t f = 0.40ns) cell name output pin maximum fanouts STD80 stdm80 pic po 91 42 y 231 137 picd po 92 42 y 237 141 picu po 91 42 y 240 130 pil pild po 91 C y 277 C pilu po 91 C y 281 C pis po 91 42 y 182 181 pisd po 91 42 y 179 150 pisu po 91 42 y 179 206 pitb po 91 C y 180 C plic po 69 C y 293 C plicd po 69 C y 317 C plicu po 69 C y 302 C plis po 69 C y 348 C plisd po 69 C y 361 C plisu po 69 C y 246 C phic po C 34 y C 141 phicd po C 34 y C 143 phicu po C 34 y C 137 phil po C 34 y C 136 phild po C 34 y C 156 philu po C 34 y C 135 phis po C 34 y C 131 phisd po C 34 y C 144 phisu po C 34 y C 145 phit phitd po C 34 y C 144 phitu po C 34 y C 148 psckdab2 y fig 1-19 (a) fig 1-20 (a) psckdab4 y fig 1-19 (b) fig 1-20 (b) psckdab6 y C fig 1-20 (c) psckdab8 y fig 1-19 (c) fig 1-20 (d) psckdab12 y fig 1-19 (d) C psosck1 psosck16 pa dy 9 6 yn 36 25 psosck2 psosck26 pady 94 62 yn 319 225 psoscm1 psoscm16 pady 1097 778 yn 888 633 psoscm2 psoscm26 pady 1097 778 yn 888 633 psoscm3 psoscm36 pady 2194 1548 yn 1596 1136 psoscm4 psoscm46 pady 4356 3010 yn 2389 1699 psoscm5 psoscm56 pady 6592 4508 yn 1257 894 psoscm6 psoscm66 pady 8923 6054 yn 4750 3369 cell name output pin maximum fanouts STD80 stdm80
introduction to STD80/stdm80 maximum fanouts sec asic 1-21 STD80/stdm80 figure 1-19. fanout (sl) vs. frequency curve of STD80 clock drivers figure 1-20. fanout (sl) vs. frequency curve of stdm80 clock drivers (a) psckdab2 ck2 (b) psckdab4 ck4 (c) psckdab8 ck8 (d) psckdab12 ck12 (a) psckdab2 ck2 (b) psckdab4 ck4 (c) psckdab6 ck6 (d) psckdab8 ck8
product line-up introduction to STD80/stdm80 STD80/stdm80 1-22 sec asic product line-up table 1-14. optimum gates vs. pad numbers on STD80/stdm80 note : chip size can be changed depending on the circuit design. packages note : the selection of a package type and pin count is dependent on the size of a chip. ref. no estimated gates total pads maximum i/o pads tlm (70%) dlm (40%) tlm dlm 01 10,000 57 75 41 59 02 15,000 70 93 54 77 03 20,000 81 107 65 91 04 30,000 99 131 83 115 05 40,000 114 151 98 135 06 50,000 128 169 112 153 07 60,000 140 186 124 170 08 70,000 151 201 135 185 09 80,000 162 214 146 198 10 90,000 172 227 156 211 11 100,000 181 240 175 224 12 120,000 198 263 182 247 13 140,000 214 284 198 268 14 160,000 229 303 213 287 15 180,000 243 322 227 306 16 200,000 256 339 240 323 17 250,000 287 379 271 363 18 300,000 314 416 298 400 19 350,000 339 449 323 433 20 400,000 363 480 347 464 21 450,000 385 509 369 493 22 500,000 406 537 390 521 type dip sdip sop plcc qfp pin count 24 28 40 42 24 28 30 32 40 42 48 54 56 64 28 32 28 32 44 68 84 44 48 60 64 80 100 128 132 160 208 240
introduction to STD80/stdm80 dedicated corner vdd/vss pads sec asic 1-23 STD80/stdm80 dedicated corner v dd /v ss pads the corner pads shown in the following ?gure are well-suited for double bonding purposes. pad 1 and pad 2 can be bonded to the same package pin. unlike normal i/o pads, these pads can only be used for v dd /v ss listed in table 1-15. use of corner pads. figure 1-21. v dd /v ss corner pads notes: 1. there is no dedicated corner vssi pad. therefore, internal v ss must be supplied using i/o pad type cell. 2. corner pads are used to reduce the power/ground noise when some parts of the design cause noise problem especially while the other parts keep quiet. table 1-15. use of corner pads external design interface considerations this section brie?y describes what you should consider when chips interface with outside world especially for a noise protection. input buffer figure 1-22. effect of schmitt trigger input buffer 1 vsso 9 vdd3o 2 vsso 10 vdd3o 3 vssi 11 vssi 4 vssi 12 vssi 5 vddi 13 vddi 6 vddi 14 vddi 7 vdd5o 15 vsso 8 vdd5o 16 vsso 1 2 3 4 8 7 6 5 9 10 11 12 16 15 14 13 (a) input signal with heavy noise (b) after ttl input buffer of which logic (c) after schmitt trigger of which positive- and v t v t v t vin vout vin vout vt+ vtC vt unwanted signal caused by noise noise spike noise spike threshold is vt negative-going threshold voltages are vt+ and vtC
external design interface considerations introduction to STD80/stdm80 STD80/stdm80 1-24 sec asic usually there are three types of input receivers in asic libraries; ttl input buffer, cmos input buffer, and various schmitt trigger input buffers. ttl input buffer has relatively poor noise characteristics because of its shifted logic threshold voltage. cmos input buffer is better than ttl against a noise because the logic threshold voltage is near 2.5volt. if an input signal has relatively large noise spikes, it could cause an unwanted input signal. when an input signal is very noisy, the noise can be ?ltered by using a schmitt trigger input buffer. as shown in figure 1-22. effect of schmitt trigger input buffer, schmitt trigger input buffers have two different input thresholds for positive- and negative-going signals. this hysteresis between positive- and negative-going voltage signals can ?lter a noisy signal to a wanted one. according to applications, the most suitable one can be chosen among the various schmitt trigger input buffers having different levels of threshold voltage. output pad cell as incoming signals to a chip have a noise, the noise can also be induced by the operation of the chip itself. there are several sources of a noise, but the greatest singular source of a noise is the switching of an output with high capacitive load. figure 1-23. simple model of output pad cell figure 1-23. simple model of output pad cell shows the simple model of an output driver considering the external interface. l1 and l2 are parasitic inductances of the package and c l is an output load. vout will fall as vin rises and the current i ?ows through n-transistor discharging the loaded charge (v dd c l ). the details of this operations are described in figure 1-24. ground bounce phenomenon. the important phenomenon which can be observed in this ?gure is that the voltage level vn shifts relative to the system ground. vn is the ground of the chip. this phenomenon is called as a ground bounce that is the chip reference shift caused by the external inductance and the transient current ?ow to the ground. the amount of voltage level shifted by the ground bounce is vn = -l (di / dt) when the output driver makes a low-to-high transition, the similar noise problem is generated on the power. figure 1-24. ground bounce phenomenon i c l : bonding pad l2 l1 vin system ground system power supply vout r l (a) vin (b) vout (c) i (d) vn t t t t i = C c l (dvout / dt) vn = l1 (di / dt)
introduction to STD80/stdm80 external design interface considerations sec asic 1-25 STD80/stdm80 the following graphs show typical ac characteristics of non-slew and slew-rate output drives in STD80/stdm80. using the slew-rate control, you can reduce the switching noise. figure 1-25. ac characteristics of non-slew and slew rate output drives ground bouncing voltage vs. time 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -13.81m 0.000 12.50m 25.00m 37.50m 50.00m 62.50m 75.00m 86.43m pob8 pob8sm 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n -36.43m -25.00m 0.000 25.00m 50.00m 75.00m 100.0m 125.0m 140.7m pob12 pob12sm pob12sh 1 w input v dd 2nh 1 w 2nh pa d 2nh 1 w < test condition >
external design interface considerations introduction to STD80/stdm80 STD80/stdm80 1-26 sec asic ground bouncing voltage vs. time 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n volt -88.49m -50.00m 0.000 50.00m 100.0m 150.0m 200.0m 220.4m pob16 pob16sm pob16sh 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n -225.7m -100.0m 0.000 100.0m 200.0m 300.0m 370.7m pob24 pob24sm pob24sh 0.000 time 2.500n 7.500n 12.50n 17.50n 20.00n -168.0m -100.0m -50.00m -7.451n 50.00m 100.0m 150.0m 200.0m 250.0m 317.2m pob20 pob20sm pob20sh
introduction to STD80/stdm80 external design interface considerations sec asic 1-27 STD80/stdm80 simultaneous switching outputs (ssos) if several output drivers switch from high to low simultaneously, the ground bouncing level becomes quite large because the current ?owing through the inductance l is the total sum of the transient current of each output driver. the amount of total current and the level of ground bounce are proportional to the number of ssos. this ground bounce can cause two types of problems, a noise margin reduction and a generation of noise spike on the output pad. noise margin reduction the ground bounce can cause a noise margin reduction when the same ground bus is used for both input buffers and output drivers as shown in figure 1-27. the figure of ssos. the noise margin reduction can be explained using the circuit in the same ?gure. as you can see, if outputs switch from high to low simultaneously, it results in a ground bounce or the rise of the chip ground level relative to system ground. the rise appears as the input voltage vin_a is below v ih causing false triggering of the input buffer. vin is, in this case, not the same as vin_a. note that vin is measured relative to the system ground, while vin_a is measured relative to the local device ground. this phenomenon is shown in figure 1-26. noise margin reduction due to ssos. for a low-to-high transition, it is the low input levels (v il ) that are affected. figure 1-26. noise margin reduction due to ssos noise spike generation on stable output if input and output power buses are separated, the problem of a noise margin reduction in the input buffer can be solved. however, ground bounce can cause another problem in spite of using separated power and ground bus. the figure 1-28. noise spike induced by ground bounce shows a common octal driver application where ground bounce spikes will be observable on the one stable output. if the spike is considered as high by another chip, this ground bounce may upset that operation of interfacing device or cause system logic errors. vin_a v ih v il v ss 2.0v 0.8v figure 1-27. the figure of ssos i c l i c l i c l i c l nxi vin vin_a system ground input receiver ssos chip ground (vn) chip power internal logic
external design interface considerations introduction to STD80/stdm80 STD80/stdm80 1-28 sec asic for example, suppose c l = 100pf, v dd = 3.3volt, t f = 5ns. from figure 1-24. ground bounce phenomenon, the maximum current ?ow occurs at time 0.5 t f . then approximately, i = c l (dv / dt) @ c l ( d v / d t), and i (max) = 100 10 -12 {5 / (2.5 10 -9 )} = 200 [ma]. if the number of ssos is 5, and l is 4nh, vn = l (di / dt) n @ l ( d i / d t) n by approximation, vn (max) = 4 10 -9 {0.200 / (2.5 10 -9 )} 5 = 1.60 [volt]. from this calculation, 1.60v of noise spike is expected. this is about logic threshold voltage of ttl. this numerical estimate clearly shows that power bus noise control is one of the fundamental problems in a high-speed cmos vlsi design. it is an important design consideration to prevent the noise from affecting the integrity of the logic operation of a chip. figure 1-28. noise spike induced by ground bounce how to protect ground bounce? the fundamental solution to the ground bounce problem is to reduce the inductance of the package. however, in the boundary of a given packaging technology, the following guidelines can be used for reducing ground bounce: (1) if possible, use separate power and ground buses for input buffers and output drivers. (2) the number of ground and power pads should not be less than the required number of pads. (3) if the design is not so much sensitive to speed, use slew rate control, i.e., increase switching time, to reduce the value of di / dt of an output driver. sec supports two levels of slew rate controlled output buffers, sm and sh. you can see this effect in the following ?gure. figure 1-29. effect on reducing peak current with slew-rate control (4) if you cannot use a slew rate cell because of the speed requirement, you can stagger the output driver as shown in figure 1-30. effect on reducing peak current with staggering output drivers. this is not a general-purpose solution. it makes sense only when special relief in timing requirements exists from a system architecture. noise spike l i t t t t 3 ssos 3 ssos v i v i
introduction to STD80/stdm80 crystal oscillator considerations sec asic 1-29 STD80/stdm80 figure 1-30. effect on reducing peak current with staggering output drivers (5) high-drive outputs should be close to v ss pins. ssos should be placed particularly close to v ss pins. (6) ssos should be appropriately placed in groups belonging to given v ss pins. (7) noise-sensitive signals such as clock, asynchronous clear and preset should be located away from ssos and high-drive outputs. also, assign them to pins with low inductance and resistance, preferably near v ss , if one is available away from ssos or high-drive outputs. (8) place ssos on low inductance pins, such as those located on the inner rows or middle positions of pgas. (9) clock, preset and clear inputs must not be placed on the corners of a package, especially when the array is packaged in dip. (10)output signals to be used as clock, preset or clear for other devices must be kept away from ssos and close to v ss pin. these guidelines assist you in choosing the best package(s) for the application. furthermore, the recommendations about pinout results in reliable and predictable devices that minimizes harmful dc and ac effects on the system. crystal oscillator considerations overview STD80/stdm80 contains a circuit commonly referred to as an on-chip oscillator. the on-chip circuit itself is not an oscillator but an ampli?er which is suitable for being used as the ampli?er part of a feedback oscillator. with proper selection of off-chip components, this oscillator circuit performs better than any other types of clock oscillators. it is very important to select suitable off-chip components to work with the on-chip oscillator circuitry. it should be noted, however, that sec cannot assume the responsibility of writing speci?cations for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the ?nished design in production, anymore than a transistor manufacturer, whose data sheets show a number of suggested ampli?er circuits, can assume responsibility for the operation, in production, of any of them. we are often asked why we dont publish a list of required crystal or ceramic resonator speci?cations, and recommend values for the other off-chip components. this has been done in the past, but sometimes with consequences that were not intended. suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. fearing that sec will not guarantee operation with 50ohm crystals, you order the expensive ones. in fact, sec guarantees only what is embodied within an sec product. besides, there is no reason why 50ohm crystals couldnt be used, if the other off-chip components are suitably adjusted. should we recommend values for the other off-chip components? should we do for 50ohm crystals or 30ohm crystals? with respect to what should we optimize their selection? should we minimize start-up time or maximize frequency stability? in many applications, neither start-up time nor frequency stability is particularly critical, and our recommendations are only restricting your system to unnecessary tolerances. it all depends on the application. t t t t 3 ssos v i v i
crystal oscillator considerations introduction to STD80/stdm80 STD80/stdm80 1-30 sec asic oscillator design considerations asic designers have a number of options for clocking the system. the main decision is whether to use the on-chip oscillator or an external oscillator. if the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? the decisions have to be based on both economic and technical requirements. in this section we will discuss some of the factors that should be considered. on-chip oscillator in most cases, the on-chip ampli?er with the appropriate external components provides the most economical solution to the clocking problem. exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. the external components that commonly used for cmos gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, c1 and c2, and two resistor rf and rx as shown in the ?gure below. figure 1-31. cmos oscillator crystal specifications speci?cations for an appropriate crystal are not very critical, unless the frequency is. any fundamental-mode crystal of medium or better quality can be used. we are often asked what maximum crystal resistance should be speci?ed. the best answer to that question is the lower the better, but use what is available. the crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it cant be compensated for by appropriate selection of the capacitances, c1 and c2. similar questions are asked about speci?cations of load capacitance and shunt capacitance. the best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such speci?cations are meaningful in your frequency tolerances are tighter than about 0.1%. part of the problem is that crystal manufacturers are accustomed to talking ppm tolerances with radio engineers and simply wont take your order until youve ?lled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. dont pay for 0.003% crystals if your actual frequency tolerance is 1%. oscillation frequency the oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. the on-chip ampli?er has little effect on the frequency, which is as it should be, since the ampli?er parameterizes temperature and process dependent. the in?uence of the on-chip ampli?er on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel c1 and c2, and the pada-to-pady (pin-to-pin) capacitance, which parallels the crystal. the input and pin-to-pin capacitances are about 7pf each. internal phase deviations capacitance of 25 to 30pf. these deviations from the ideal have less effect in the positive reactance oscillator (with the inverting ampli?er) than in a comparable series resonant oscillator (with the non-inverting ampli?er) for two reasons: ?rst, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. c1 c2 rx rf pada pady feedback inside of a chip amplifier
introduction to STD80/stdm80 crystal oscillator considerations sec asic 1-31 STD80/stdm80 c1 / c2 selection optimal values for the capacitors c1 and c2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-speci?c requirements on start-up time and frequency tolerance. start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. as a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. considerations of both start-up time and frequency stability over temperature suggest that c1 and c2 should be about equal and at least 20pf. (but they dont have to be either.) increasing the value of these capacitances above some 40 or 50pf improves frequency stability. it also tends to increase the start-up time. these is a maximum value (several hundred ph, depending on the value of r1 of the quartz or ceramic resonator) above which the oscillator wont start up at all. if the on-chip ampli?er is a simple inverter, the user can select values for c1 and c2 between some 20 and 100pf, depending on whether start-up time or frequency stability is the more critical parameter in a speci?c application. rf / rx selection a cmos inverter might work better in this application since a large rf (1mega-ohm) can be used to hold the inverter in its linear region. logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. for that reason a resistor rx (several k-ohm) is often added to the feedback network, as shown in figure 1-31. cmos oscillator. at higher frequencies a 20 or 30pf capacitor is sometimes used in the rx position, to compensate for some of the internal propagation delay. pin capacitance internal pin-to-ground and pin-to-pin capacitances, and pada and pady have some effect on the oscillator. these capacitances are normally taken to be in the range of 5 to 10pf, but they are extremely dif?cult to evaluate. any measurement of one such capacitance necessarily include effects from the others. one advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. we would suggest that there is little justi?cation for more precision than to assign them a value of 7pf (pada-to-ground and pada-to-pady). this value is probably not in error by more than 3 or 4pf. the pady-to-ground cap. is not entirely a pin capacitance, but more like an equivalent output capacitance of some 25 to 30pf, having to include the effect of internal phase delays. this value varies to some extent with temperature, process, and frequency. placement of components noise glitches arising at pada or pady pins at the wrong time can cause a miscount in the internal clock-generating circuitry. these kinds of glitches can be produced through capacitive coupling between the oscillator components and pcb traces carrying digital signals with fast rise and fall times. for this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the pada, pady, and v ss pins. if possible, use dedicated v ss and v dd pin for only crystal feedback ampli?er.
crystal oscillator considerations introduction to STD80/stdm80 STD80/stdm80 1-32 sec asic troubleshooting oscillator problems the ?rst thing to consider in case of dif?culty is that there may be signi?cant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. noise glitches, that are not present in the test jig but are in the application board, are another possibility. capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. inductive coupling is also doubtful, if there is strong current nearby. these problems are a function of the pcb layout. surrounding oscillator components with quit traces (for example, vcc and ground) will alleviate capacitive coupling to signals having fast transition time. to minimize inductive coupling, the pcb layout should minimize the areas of the loops formed by oscillator components. the loops demanding to be checked are as follows: pada through the resonator to pady; pada through c1 to the v ss pin; pady through c2 to the v ss pin. it is not unusual to ?nd that the ground ends of c1 and c2 eventually connect up to the v ss pin only after looping around the farthest ends of the board. not good. finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. never underestimate the perversity of a software problem.

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